1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly, to an impedance adjustment circuit which can adjust output impedance, input impedance, etc., an impedance adjustment method, and a semiconductor device comprising this impedance adjustment circuit.
2. Description of the Related Art
A high-speed interface is required to function as a sending circuit, a receiving circuit, a transmission line between LSIs, and a distributed constant circuit, and at the same time impedance matching is indispensable for a high-speed interface. The reason is that mismatch between the impedance of a transmission line and the impedance of a load causes a reflected wave, which then invites errors of an input buffer.
Accordingly, a conventional output buffer circuit which performs a high-speed interface function has a built-in resistor at the output side thereof inside an LSI, or has a resistor connected thereto outside the LSI.
According to the method of providing a built-in resistor inside an LSI or providing an external resistor for impedance matching, it is necessary to increase the value of resistance of a resistance element which is not susceptible to influences caused by temperature fluctuation, power supply voltage fluctuation, and process fluctuation, and to enlarge the size of a driver-use MOS transistor in order to make the resistance of the MOS transistor relatively small.
However, if the size of the MOS transistor is enlarged, the LSI will cause a problem that its performance is deteriorated, because of deterioration of mountability inside the LSI, increase in penetrating currents, increase in noises, increase in the amount of electricity consumed, etc.
To cure these adverse influences, recent LSIs have a built-in impedance adjustment circuit. The major adjustment method implemented by such an impedance adjustment circuit is to match the output impedance of an output buffer with an external resistance element having a high degree of precision.
For example, Unexamined Japanese Patent Application KOKAI Publication No. 2001-94048, Unexamined Japanese Patent Application KOKAI Publication No. 2000-183717, Unexamined Japanese Patent Application KOKAI Publication No. H8-321769, Unexamined Japanese Patent Application KOKAI Publication No. H8-32435, and Unexamined Japanese Patent Application KOKAI Publication No. H11-55106 disclose a system for adjusting the impedance of a transistor group (dummy buffer circuit) including one or a plurality of MOS transistors having the same configuration as that of an output buffer by using a comparator and a counter.
Unexamined Japanese Patent Application KOKAI Publication No. 2001-217705 discloses a system for performing impedance adjustment by measuring the impedance of a signal output from an output buffer.
Unexamined Japanese Patent Application KOKAI Publication No. H11-17518 discloses a configuration provided with a dummy transmission line to which an output signal from an output buffer is transmitted, for performing impedance adjustment in consideration of also a change in the impedance that has occurred in the dummy transmission line.
Unexamined Japanese Patent Application KOKAI Publication No. 2001-168704 discloses a system provided with a timer circuit, a logic activation circuit, and an impedance fluctuation detection circuit, for re-performing impedance adjustment after a certain time elapses, to cover fluctuation of the value of resistance caused by a rise of temperature inside the LSI during operation.
Unexamined Japanese Patent Application KOKAI Publication No. 2001-94409 discloses a configuration with improved mountability, improved noiselessness, and reduced amount of electricity consumed, achieved by connecting the same external resistance terminal to both of a PMOS transistor impedance adjustment circuit and an NMOS transistor impedance adjustment circuit.
The contents of these publications are incorporated herein.
With advanced high-speeding of interfaces, a higher-degree of precision of impedance adjustment by an impedance adjustment circuit is required for an output buffer which connects LSIs with each other. Therefore, it is necessary to reduce unevenness in the adjusted impedance to make the impedance accurately coincide with the level of the external resistance.
Therefore, for example, a detector (comparator) is required to have a high degree of detection precision.
However, since an impedance adjustment circuit is placed inside an LSI, it might cause errors due to noises (power source noises, etc.) caused by itself or noises received from surrounding circuits. That is, it is important to remove errors caused by these noises to improve the detection precision.
For example, the degree of precision in detecting a potential required of a comparator is around several mV, when the power supply voltage is 1V.
However, since a noise in an LSI has around several ten mV, errors will be caused if a noise is mixed into a detection signal from the comparator.
When considering the above-described prior art in view of this point, each of them is a system having a view to raising the detection precision of a detector, but not a system having a view to reducing errors caused by noises, or a system capable of reducing influences of errors caused by noises.